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W9725G6IB
1. GENERAL DESCRIPTION
The W9725G6IB is a 256M bits DDR2 SDRAM, organized as 4,194,304 words × 4 banks × 16 bits.
This device achieves high speed transfer rates up to 800Mb/sec/pin (DDR2-800) for general
applications. W9725G6IB is sorted into two speed grades: -25 and -3. The -25 is compliant to the
DDR2-800 (6-6-6) specification, the -3 is compliant to the DDR2-667 (5-5-5) specification.
All of the control and address inputs are synchronized with a pair of externally supplied differential
clocks. Inputs are latched at the cross point of differential clocks (CLK rising and CLK falling). All
I/Os are synchronized with a single ended DQS or differential DQS- DQS pair in a source
synchronous fashion.
2. FEATURES
Power Supply: V DD , V DDQ = 1.8 V ± 0.1 V
Double Data Rate architecture: two data transfers per clock cycle
CAS Latency: 3, 4, 5 and 6
Burst Length: 4 and 8
Bi-directional, differential data strobes (DQS and DQS ) are transmitted / received with data
Edge-aligned with Read data and center-aligned with Write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CLK and CLK )
Data masks (DM) for write data
Commands entered on each positive CLK edge, data and data mask are referenced to both edges
of DQS
Posted CAS programmable additive latency supported to make command and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal
quality
Auto-precharge operation for read and write bursts
Auto Refresh and Self Refresh modes
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = Read Latency - 1 (WL = RL - 1)
Interface: SSTL_18
Packaged in WBGA 84 Ball (8X12.5 mm 2 ), using Lead free materials with RoHS compliant
Publication Release Date: Oct. 23, 2009
-4-
Revision A04
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相关代理商/技术参数
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